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| AdderSubtractor |
- Adder-Subtractor Circuit
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| Adder Subtractor Circuit diagram |
- VHDL Code
--XOR Logic gate program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity XOR_gate is
Port ( c : out STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC);
end XOR_gate;
architecture Behavioral of XOR_gate is
begin
c <= a xor b;
end Behavioral;
--Full Adder program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
port(a,b,cin : in std_logic;
s,cout : out std_logic);
end FA;
architecture functional of FA is
begin
s <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (cin and a);
end functional;
--Half Adder program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HA is
port(a,b : in std_logic;
s,c : out std_logic);
end HA;
architecture functional of HA is
begin
s <= a xor b;
c <= a and b;
end functional;
--Adder-Subtractor program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity AddorSub is
port(x,y : in std_logic_vector(3 downto 0);
S : in std_logic;
z : out std_logic_vector(3 downto 0);
cout : out std_logic);
end AddorSub;
architecture Behavioral of AddorSub is
signal b : std_logic_vector(3 downto 0);
signal c : std_logic_vector(4 downto 0);
signal m : std_logic_vector(4 downto 0);
signal r : std_logic_vector(3 downto 0);
signal k : std_logic_vector(3 downto 0);
component FA
port(a,b,cin : in std_logic;
s,cout : out std_logic);
end component;
component XOR_gate
Port ( c : out STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC);
end component;
component HA
port(a,b : in std_logic;
s,c : out std_logic);
end component;
begin
f1 : for i in 0 to 3 generate
x1 : XOR_gate port map(b(i),y(i),S);
end generate;
c(0) <= S;
f2 : for i in 0 to 3 generate
a1: FA port map(x(i),b(i),c(i),r(i),c(i+1));
end generate;
cout <= c(4);
m(0) <= '1';
f3 : for i in 0 to 3 generate
a2 : HA port map((not r(i)),m(i),k(i),m(i+1));
end generate;
with ((not c(4)) and S) select z <= k when '1',
r when others;
end Behavioral;
- Simulation Results
Addition, x = "1111", y = "1000", result = cout&z(3 downto 0) = "10111"
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| Addition , verification phase |
Subtraction, x=4'b0011, y=4'b1000, result = - 4'b0101 = -5
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| Subtraction, verification phase |
- VERILOG Code
//Full Adder verilog program
module fa(
output s,
output cout,
input a,
input b,
input cin
);
assign s = a ^ b ^ cin;
assign cout = (a & b)|(b & cin)|(cin & a);
endmodule
//Adder-Subtractor verilog program
module adding_S_0(
output [3:0]z,
output cout,
input [3:0]a,
input [3:0]b,
input S
);
wire [3:0]y;
wire [3:0]c;
wire [3:0]r;
assign c[0] = S;
xor x1(y[0],S,b[0]);
fa f1(.s(r[0]),.cout(c[1]),.a(a[0]),.b(y[0]),.cin(c[0]));
xor x2(y[1],S,b[1]);
fa f2(.s(r[1]),.cout(c[2]),.a(a[1]),.b(y[1]),.cin(c[1]));
xor x3(y[2],S,b[2]);
fa f3(.s(r[2]),.cout(c[3]),.a(a[2]),.b(y[2]),.cin(c[2]));
xor x4(y[3],S,b[3]);
fa f4(.s(r[3]),.cout(cout),.a(a[3]),.b(y[3]),.cin(c[3]));
assign z = ((~cout)&S)?((~r)+1):r;
endmodule
- Simulation Results
Addition, x = "1111", y = "1000", result = cout&z(3 downto 0) = "10111"
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| Addition, verification phase |
Subtraction, x=4'b0011, y=4'b1000, result = - 4'b0101 = -5
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| subtraction, verification phase |
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