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| Memory Elements |
- MEMORY ELEMENTS:
The Combinational circuit can be defined as a circuit whose output is dependent only on the inputs at the same instant of time where as a sequential circuit can be defined as a circuit whose output depends not only on the present inputs but also on the past history of inputs. In other words the output of a sequential circuit may depend upon its previous outputs and so in effect has some form of "memory". The mathematical model of a sequential circuit is usually referred to as a sequential machine.
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| Sequential circuits |
- S-R flipflop
Block diagram
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| flipflop |
Internal logic
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| functionality |
Truth table
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| Q - previous state |
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity s_r_ff_vhdl is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
clock : in STD_LOGIC;
Q : out STD_LOGIC;
not_Q : out STD_LOGIC);
end s_r_ff_vhdl;
architecture Behavioral of s_r_ff_vhdl is
begin
process(clock,S,R)
variable state : std_logic;
begin
if(clock'event and clock = '1') then
if(S = '0' and R = '0') then
state := state;
elsif(S = '0' and R = '1') then
state := '0';
elsif(S = '1' and R = '0') then
state := '1';
else
state := 'Z';
end if;
end if;
Q <= state;
not_Q <= not state;
end process;
end Behavioral;
SIMULATION RESULTS (XILINX ISE EDA Tool & ISIM simulator)
 |
| verification phase |
VERILOG Code
module S_R_flipflop(
input S,
input R,
input clock,
output reg Q,
output reg not_Q
);
initial
begin
Q <= 1'b0;
not_Q <= 1'b1;
end
always @(posedge clock)
begin
case({S,R})
2'b00: begin
Q <= Q;
not_Q <= not_Q;
end
2'b01: begin
Q <= 1'b0;
not_Q <= 1'b1;
end
2'b10: begin
Q <= 1'b1;
not_Q <= 1'b0;
end
2'b11: begin
Q <= 1'bx;
not_Q <= 1'bx;
end
endcase
end
endmodule
SIMULATION RESULTS (XILINX ISE EDA Tool &
ISIM simulator
)
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| verification phase |
- D-flipflop
Block diagram
 |
| block of d-flipflop |
Internal logic & Truth table
 |
| logic's |
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
Port ( D : in STD_LOGIC;
clock : in STD_LOGIC;
Q : out STD_LOGIC;
not_Q : out STD_LOGIC);
end d_ff;
architecture Behavioral of d_ff is
begin
process(clock)
begin
if(clock'event and clock = '1') then
Q <= D;
not_Q <= not D;
end if;
end process;
end Behavioral;
SIMULATION RESULTS (XILINX ISE EDA Tool &
ISIM simulator
)
 |
| verification phase |
VERILOG Code
module D_Flipflop(
input D,
input clock,
output reg Q,
output reg not_Q
);
always @(posedge clock)
begin
Q <= D;
not_Q <= ~D;
end
endmodule
SIMULATION RESULTS (XILINX ISE EDA Tool &
ISIM simulator
)
 |
| verification phase |
- J-K Flipflop
Block Diagram
 |
| block |
Internal Logic
 |
| logic's |
Truth Table
 |
| functionality |
VHDL Code (Xilinx ISE 14.5 EDA Tool)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity j_k_flipflop_vhdl_code is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
clock : in STD_LOGIC;
Q : out STD_LOGIC;
not_Q : out STD_LOGIC);
end j_k_flipflop_vhdl_code;
architecture Behavioral of j_k_flipflop_vhdl_code is
begin
process(clock,J,K)
variable state : std_logic;
begin
if(clock'event and clock = '1') then
if(J = '0' and K = '0') then
state := state;
elsif(J = '0' and K = '1') then
state := '0';
elsif(J = '1' and K = '0') then
state := '1';
else
state := not state;
end if;
end if;
Q <= state;
not_Q <= not state;
end process;
end Behavioral;
Simulation Results (ISIM simulator)
 |
| verification |
Verilog Code (Xilinx ISE 14.5 EDA Tool)
module J_K_FLIPFLOP(
input J,
input K,
input clock,
output reg Q,
output reg not_Q
);
initial
begin
Q <= 1'b0;
not_Q <= 1'b1;
end
always @(posedge clock)
begin
case({J,K})
2'b00: begin
Q <= Q;
not_Q <= not_Q;
end
2'b01: begin
Q <= 1'b0;
not_Q <= 1'b1;
end
2'b10: begin
Q <= 1'b1;
not_Q <= 1'b0;
end
2'b11: begin
Q <= ~Q;
not_Q <= Q;
end
endcase
end
endmodule
Simulation Results (ISIM simulator)
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| verification |
- T-Flipflop
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| block |
 |
| Logic's |
 |
| functionality |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_flipflop_vhdl_code is
Port ( T : in STD_LOGIC;
clock : in STD_LOGIC;
Q : out STD_LOGIC;
not_Q : out STD_LOGIC);
end T_flipflop_vhdl_code;
architecture Behavioral of T_flipflop_vhdl_code is
begin
process(clock,T)
variable state : std_logic :='0';
begin
if(clock'event and clock = '1') then
if(T = '0') then
state := state;
else
state := not state;
end if;
end if;
Q <= state;
not_Q <= not state;
end process;
Simulation Results (ISIM Simulator)
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| verification |
Verilog Code
module T_FLIPFLOP(
input T,
input clock,
output reg Q,
output reg not_Q
);
initial
begin
Q <= 1'b0;
not_Q <= 1'b1;
end
always @(posedge clock)
begin
case(T)
1'b0: begin
Q <= Q;
not_Q <= not_Q;
end
1'b1: begin
Q <= ~Q;
not_Q <= Q;
end
endcase
end
endmodule
Simulation Results (ISIM simulator)
 |
| verification |
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