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| 3bit Counter |
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| FSM diagram |
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| Data Flow |
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| Truth Table |
Verilog Code:
module UpDown_Counter_loopFilter( up_dn, CLK, up_dn_counter );
input up_dn;
input CLK;
output reg [2:0] up_dn_counter;
initial
begin
up_dn_counter = 3'b000;
end
always @(posedge CLK)
begin
if (up_dn == 1'b1)
begin
up_dn_counter = up_dn_counter + 1'b1;
end
else if (up_dn == 1'b0)
begin
up_dn_counter = up_dn_counter - 1'b1;
end
end
endmodule
Waveform : (simulation)
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