 |
| Subtractors |
- Half Subtractor
IC Block
 |
| IC diagram |
Internal Logic
 |
| Logic's |
Truth Table
 |
| functionality |
VHDL Code
entity HS is
port(a,b : in std_logic;
d,bo : out std_logic);
end HS;
architecture Behavioral of HS is
begin
d <= a xor b;
bo <= (not a) and b;
end Behavioral;
Verilog Code
module hs(
output d,
output bo,
input a,
input b
);
assign d = a ^ b;
assign bo = (~a) & b;
endmodule
Simulation Results
 |
| verification phase |
- Full Subtractor
IC Block
 |
| block |
Internal Logic
 |
| logic's -> c = Bin |
Truth Table
 |
| functionality |
VHDL Code
entity FS is
port(a,b,bin : in std_logic;
d,bo : out std_logic);
end FS;
architecture Behavioral of FS is
begin
d <= a xor b xor bin;
bo <= (bin and (not(a xor b))) or ((not a)and b);
end Behavioral;
Verilog Code
module fs(
output d,
output bo,
input a,
input b,
input bin
);
assign d = a ^ b ^ bin;
assign bo = (bin & (~(a ^ b)))|((~a)&b);
endmodule
Simulation Results
 |
| verification phase |
- n-bit Subtractor(n = 4-bit)
IC block (4-bit)
 |
| 4-bit Subtractor |
VHDL Code
entity BIT_4_SUB is
generic(n : integer := 4);
port(x,y : in std_logic_vector(n-1 downto 0);
bin : in std_logic;
r : out std_logic_vector(n-1 downto 0);
bout : out std_logic);
end BIT_4_SUB;
--component is similar to the above FS entity
architecture Behavioral of BIT_4_SUB is
component FS
port(a,b,bin : in std_logic;
d,bo : out std_logic);
end component;
signal b : std_logic_vector(n downto 0);
begin
b(0) <= bin;
f1: for i IN 0 to n-1 generate
p1: FS port map(x(i),y(i),b(i),r(i),b(i+1));
end generate;
bout <= b(n);
end Behavioral;
Verilog Code
module bit_4_subtractor(r,bout,x,y,bin
);
parameter n = 4;
output [n-1:0] r;
output bout;
input [n-1:0] x;
input [n-1:0] y;
input bin;
assign {bout,r} = x-y-bin;
endmodule
Simulation Results
 |
| verification phase |
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