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Sign Extend

Sign Extend


Block diagram of Sign Extend

Figure.1 Block diagram of Sign Extend



VERILOG Code

module sign_extend(
    output reg [31:0] y,
    input [15:0] x/*,
input clock*/
    );
always @(/*posedge clock*/ x)
begin
if(x[15] == 1'b1)
begin
y[31:16] <= 16'b1111111111111111;
y[15:0] <= x[15:0];
end
else if(x[15] == 1'b0)
begin
y[31:16] <= 16'b0000000000000000;
y[15:0] <= x[15:0];
end
else
begin
y[31:16] <= 16'bxxxxxxxxxxxxxxxx;
y[15:0] <= x[15:0];
end
end
endmodule



Theoretical Results
Input: X =16’b1000011111001100
Output: Y = 32’b11111111111111111000011111001100



Simulation Result for Sign Extend


Figure.2 Simulation Results for Sign Extend


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