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| ASIC Design Types |
The IC which is called the integrated Circuit, the connections of several basic gates like AND, OR, XOR, XNOR, NOT, NOR, NAND intended to perform a logical function. If the IC is targetted for a specific purpose then it is called as the ASIC - Application Specific Integrated Circuit. Some of the ASIC chips are a modem chip, a microcontroller, a microprocessor, a mobile RF chip, a IO controller chip, a memory channel/interface chip, the IMU (inertial measurement unit) chip, a bluetooth chip, WLAN/WiFi chip, automobile speedometer chip, an ATM/smart card enable chip, an electronic home appliance chip etc.,
The SOC chip is the integration of processor, GPU, power management unit, IO controllers (USB, HDMI, ethernet etc.,), memory bank, RF chip etc., All the SOC chips can be called as ASIC but vice-versa is not. The ASIC design is generally carried in 3 streams: DIGITAL, ANALOG & MIXED-SIGNAL.
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| ASIC design types tree |
ASIC design is carried in 3 major types :
1. FULL CUSTOM
2. SEMI CUSTOM
3. PROGRAMMABLE DESIGN
1. FULL CUSTOM:
In the full custom design, from the top level design to till the transistor level W/L is controlled by doing custom layout optimization. The design cycle time is more. Since, the design is custom optimized, the performance of the circuit is high & the power consumption is very less. The area is also saved more in this full custom, so that the chip is smaller in size. The Full custom design is carried for the standard cells (library development team), Analog team in designing the op-amp, pll, adc/dac, custom switches, analog pads etc.,
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| std cell layout |
In the semi custom design, there are 2 types:
a. Std Cell Based
b. Gate Array
i. channeled
ii. channel-less
iii. structured
The Std cell based design is most preferrably used in the commercial ASIC development world as the design cycle time is moderate. Here, the std cells are designed and developed fully custom by the std cell library development team in sync with the PDK (process development kit). The pre-designed std cells are re-used by the ASIC designers to deveop the full chip. The designers here consume the std cell family which contains cells like flip-flop, latches, and, nand, nor, xor, xnor, not, buf, mux, complex gates - aoi,oai etc., and proceed the design cycle from logic-synthesis -> floorplan -> place -> cts -> route -> eco -> layout verification -> pre silicon validation -> fabrication -> post silicon validation -> bulk production -> marketting. The std cells here are the basic building blocks whose contents are hard. The designers here achieve better performance and area by optimizating the placement of std cells in desired locations(std cell rows) mostly though EDA tools. Perform clock tree synthesis (CTS) and route with PDK allowed layers and DRC rules.
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| std cell placement |
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| routing |
The gate array based design is a pre-fabricated chip with all the logic gates pre-developed on the silicon at fixed locations. The interconnections are not fabricated. The logic gates are fabricated in arrays. The designers here choose required cell from the array library for use. With these types are design, the cycle time is very less. The channeled gate array design has a channel between the std cell rows. The channel-less gate array design is continuous in std cell rows without any channel. The structured gate array design is the combination of both channeled & channel-less. The designers here are allowed to only make interconnections and their optimizations.
3. PROGRAMMABLE DESIGN:
The Programmable logic design (PLD) chips contains the programmable switches that allow the internal circuitry in the chip to be configured and used for the targetted function. Though these designs support programming and re-using, it has dis-advatnages like circuit-complexity, high-purchase cost, lack of integrating additional blocks etc., examples: PLA, PAL, EPROM, EEPROM etc., When the logic connections are electrically fused then the function remains even when voltage is turned off. The FPGA are the field programmable gate arrays, these are mostly used as proto-type's in RTL verification/simmulation process. Here the function programmed is lost when voltage is turned off.
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| PAL |
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| FPGA |
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