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| Leap Year detecting circuit |
A combinational circuit works on the principles of Boolean logic and whose output depends upon the logical input changes at zero instance of time are called as combinational circuit. Combinational logic is used in digital world to do Boolean algebra on input signals and on stored data. In these circuits the output depends on the current input combinations.
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| combinational circuits |
The input given to the present circuit will be the year which can be represented in bcd form. It is expected to have a 4digit decimal and in bcd we have a total of 16bits and 4bits to each corresponding decimal digit.
The (d3 d2 d1 d0) be the 4digit - decimal input (year) which can be (b15 b14 b13 b12) (b11 b10 b9 b8) (b7 b6 b5 b4) (b3 b2 b1 b0) in bcd format - 16bits.
The concept in this circuit is that division by 2 is right shift by 1bit and the division by 4 is right shift by 2bits.
In this circuit I developed a two bit adder where the one set of inputs to this is the two bits in LSB (lsb and lsb+1) and the other set is decided by the (lsb+4)th bit i.e, if it is 1 then "10" else "00" is selected.
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| processing mechanism |
Circuit developed for leap year detection
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| leap year detecting circuit |
VHDL Code:
-- code for spl. 2bit adder and anding logic block (bottom module)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity spl_2_bit_adder is
Port ( bcd : in STD_LOGIC_VECTOR (2 downto 0);
z : out STD_LOGIC);
end spl_2_bit_adder;
architecture Behavioral of spl_2_bit_adder is
signal x : std_logic_vector(1 downto 0);
signal r : std_logic_vector(1 downto 0);
signal c : std_logic_vector(2 downto 0);
begin
process(bcd)
begin
if(bcd(2) = '0') then
x <= "00";
elsif(bcd(2) = '1') then
x <= "10";
else
x <= "XX";
end if;
end process;
c(0) <= '0';
l1: for i in 0 to 1 generate
r(i) <= x(i) xor bcd(i) xor c(i);
c(i+1) <= (x(i) and bcd(i)) or (bcd(i) and c(i)) or (c(i) and x(i));
end generate l1;
z <= not(r(0) or r(1));
end Behavioral;
-- Top module for leap circuit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity leaping_circuit is
Port ( bcd : in STD_LOGIC_VECTOR (15 downto 0);
z : out STD_LOGIC);
end leaping_circuit;
architecture Behavioral of leaping_circuit is
component spl_2_bit_adder
Port ( bcd : in STD_LOGIC_VECTOR (2 downto 0);
z : out STD_LOGIC);
end component;
signal x : std_logic_vector(2 downto 0);
signal y : std_logic_vector(2 downto 0);
signal r : std_logic_vector(1 downto 0);
begin
x(1 downto 0) <= bcd(1 downto 0);
x(2) <= bcd(4);
y(1 downto 0) <= bcd(9 downto 8);
y(2) <= bcd(12);
s1: spl_2_bit_adder PORT MAP(x,r(0));
s2: spl_2_bit_adder PORT MAP(y,r(1));
process(r)
begin
if(bcd(15 downto 0) = "0000000000000000") then
z <= '0';
elsif(bcd(7 downto 0) = "00000000") then
z <= r(1);
else
z <= r(0);
end if;
end process;
end Behavioral;
VERILOG Code:
// bottom module for have a spl. 2-bit adder and anding logic
module a_2_bit_adder_for_leap(
input [2:0] b,
output reg z
);
reg [1:0]a;
reg [2:0]c;
reg [1:0]r;
integer i;
always@(b)
begin
if(b[2] == 1'b0)
begin
a = 2'b00;
end
else
begin
a = 2'b10;
end
c[0] = 1'b0;
for(i = 0; i < 2 ; i = i+1)
begin
r[i] = a[i] ^ b[i] ^ c[i];
c[i+1] = (a[i]&b[i]) | (b[i]&c[i]) | (c[i]&a[i]);
end
z <= ~(r[1] | r[0]);
end
endmodule
//top module for the leaping cicuit
module combinational_leap_year(
input [15:0] bcd,
output reg L
);
wire [1:0]k;
a_2_bit_adder_for_leap a1(.b({bcd[12],bcd[9:8]}),.z(k[0]));
a_2_bit_adder_for_leap a2(.b({bcd[4],bcd[1:0]}),.z(k[1]));
always@(k)
begin
if(bcd[15:0]==0)
begin
L <= 1'b0;
end
else if(bcd[7:0]==8'b00000000)
begin
L <= k[0];
end
else
begin
L <= k[1];
end
end
endmodule
SIMULATION RESULTS : ( Xilinx ISE 14.5 EDA tool and ISIM simulator was used)
cases checked, for years 2000,2600,100,400,2016 => Z = 1,0,0,1,1 ( 1-leap year & 0-not a leap year)
For VHDL case :
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| vhdl verification phase |
For VERILOG case :
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| verilog verification phase |
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