Adding block(during J-type Instruction the branch address is evaluated)
Block diagram for Adding Block
Figure.1 Block diagram of Adding block
VERILOG Code
module adding_block(
output reg [31:0] r,
input [31:0] y,
input [31:0] x
);
always @(x,y)
begin
r <= x+y;
end
endmodule
Theoretical Results
Inputs : X = 32’h98765432
Y = 32’h98765432
Output: r = 32’h30eca864
Simulation Result for Adding Block
Figure.2 Simulation result for Adding block
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