Shifting Left
Block diagram of Shifting Left
Figure.1 Block Diagram of Shifting Left
VERILOG Code
module shifting_left(
output reg [31:0] Y,
input [31:0] X/*,
input clock*/
);
always @(/*posedge clock*/X)
begin
Y <= X<<2;
end
endmodule
Theoretical Results
Inputs: X = 32’b11111000000000000000011111001111
Outputs: Y = 32’b11100000000000000001111100111100
Simulation Result for Shifting Left
Figure.2 Simulation results for Shifting Left
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