Shifting Left 2 in J-type
Block diagram of shifting left 2 in J-type
Figure.19 Block diagram of shifting left2 in J-type
VERILOG code
module shit_left_2_in_J_type(
output reg [27:0] Y,
input [25:0] X/*,
input clock*/
);
always @(/*posedge clock*/X)
begin
Y <= X<<2;
end
endmodule
Theoretical Results
Input: x 26’b11111010101011110111101011
Output: y = 28’b1111101010101111011110101100
Simulation Result for shifting left 2 in J-type
Figure.2 Simulation result for shifting left 2 in J-type
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