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Demultiplexer's

Demultiplexer

  • DEMULTIPLEXER's
                                                                   General IC Block

general block

                                                 The data distributor, known more commonly as a Demultiplexer or Demux for short, is the exact opposite of the Multiplexer we saw in the previous tutorial. The demultiplexer takes one single input data line and then switches it to any one of a number of individual output lines one at a time. The demultiplexer converts a serial data signal at the input to a parallel data at its output lines. A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs. It has only one input, n outputs, m select input. At a time only one output line is selected by the select lines and the input is transmitted to the selected output line. A de-multiplexer is equivalent to a single pole multiple way switch.

  • 1 to 2 Demux
IC Block
1 to 2  demux block

Internal logic
logic gates

Truth Table
functionality
VHDL Code
entity demux_1to2 is
    Port ( Y : out  STD_LOGIC_VECTOR (1 downto 0);
           D : in  STD_LOGIC;
           S : in  STD_LOGIC;
           E : in  STD_LOGIC);
end demux_1to2;

architecture Behavioral of demux_1to2 is

begin
process(D,S,E)
begin
if(E = '1') then
if(S = '0') then
Y(0) <= D;
Y(1) <= '0';
elsif(S = '1') then
Y(0) <= '0';
Y(1) <= D;
else
Y <= "XX";
end if;
else
Y <= "XX";
end if;
end process;
end Behavioral;

VERILOG Code
module demux_1_2(
    output reg [1:0] Y,
    input D,
    input S,
    input E
    );
always @(D,S,E)
begin
if(E == 1'b1)
begin
if(S == 1'b1)
begin
Y[1] <= D;
Y[0] <= 1'b0;
end
else if(S == 1'b0)
begin
Y[1] <= 1'b0;
Y[0] <= D;
end
else
Y <= 2'bxx;
end
else
Y <= 2'bxx;
end
endmodule

Simulation Results
verification phase


  • 1 to 4 Demux
    IC Block
IC block
Internal Logic
 logic
Truth Table
functional logic
VHDL Code



entity demux_1to4 is
    Port ( Y : out  STD_LOGIC_VECTOR (3 downto 0);
           S : in  STD_LOGIC_VECTOR (1 downto 0);
           D : in  STD_LOGIC);
end demux_1to4;

architecture Behavioral of demux_1to4 is
begin
process(S,D)
begin
if(S = "00") then
Y(0) <= D;
Y(3 downto 1) <= "000";
elsif(S = "01") then
Y(1) <= D;
Y(0) <= '0';
Y(3 downto 2) <= "00";
elsif(S = "10") then
Y(2) <= D; 
Y(3) <= '0'; 
Y(1 downto 0) <= "00";
elsif(S = "11") then
Y(3) <= D;
Y(2 downto 0) <= "000";
else 
Y <= "XXXX";
end if;
end process;
end Behavioral;

VERILOG Code

module demux_1_4(
    output reg [3:0] Y,
    input [1:0] S,
    input D
    );

always @(S,D)
begin
case(S)
2'b00:
begin
Y[0] <= D;
Y[3:1] <= 3'b000;
end
2'b01:
begin
Y[1] <= D;
Y[3:2] <= 2'b00;
Y[0] <= 1'b0;
end
2'b10:
begin
Y[2] <= D;
Y[3] <= 1'b0;
Y[1:0] <= 2'b00;
end
2'b11:
begin
Y[3] <= D;
Y[2:0] <= 3'b000;
end
default: Y <= 4'bxxxx;
endcase
end
endmodule

Simulation Results
verification phase
  • 1 to 8 Demux
 IC Block
IC
Internal logic
logic's
Truth Table
functionality
VHDL Code
entity demux_1to8 is
    Port ( Y : out  STD_LOGIC_VECTOR (7 downto 0);
           S : in  STD_LOGIC_VECTOR (2 downto 0);
           D : in  STD_LOGIC);
end demux_1to8;

architecture Behavioral of demux_1to8 is
begin
process(S,D)
begin
if(S = "000") then
Y(0) <= D;
Y(7 downto 1) <= "0000000";
elsif(S = "001") then
Y(1) <= D;
Y(0) <= '0';
Y(7 downto 2) <= "000000";
elsif(S = "010") then
Y(2) <= D;
Y(7 downto 3) <= "00000";
Y(1 downto 0) <= "00";
elsif(S = "011") then
Y(3) <= D;
Y(2 downto 0) <= "000";
Y(7 downto 4) <= "0000";
elsif(S = "100") then
Y(4) <= D;
Y(3 downto 0) <= "0000";
Y(7 downto 5) <= "000";
elsif(S = "101") then
Y(5) <= D;
Y(4 downto 0) <= "00000";
Y(7 downto 6) <= "00";
elsif(S = "110") then
Y(6) <= D;
Y(5 downto 0) <= "000000";
Y(7) <= '0';
elsif(S = "111") then
Y(7) <= D;
Y(6 downto 0) <= "0000000";
else
Y <= "XXXXXXXX";
end if;
end process;

end Behavioral;

VERILOG Code
module demux_1_8(
    output reg [7:0] Y,
    input [2:0] S,
    input D
    );

always @(S,D)
begin
case(S)
3'b000:
begin
Y[0] <= D;
Y[7:1] <= 7'b0000000;
end
3'b001:
begin
Y[1] <= D;
Y[7:2] <= 6'b000000;
Y[0] <= 1'b0;
end
3'b010:
begin
Y[2] <= D;
Y[7:3] <= 5'b00000;
Y[1:0] <= 2'b00;
end
3'b11:
begin
Y[3] <= D;
Y[2:0] <= 3'b000;
Y[7:4] <= 4'b0000;

end
3'b100:
begin
Y[4] <= D;
Y[3:0] <= 4'b0000;
Y[7:5] <= 3'b000;
end
3'b101:
begin
Y[5] <= D;
Y[4:0] <= 5'b00000;
Y[7:6] <= 2'b00;
end
3'b110:
begin
Y[6] <= D;
Y[5:0] <= 6'b000000;
Y[7] <= 1'b0;
end
3'b111:
begin
Y[7] <= D;
Y[6:0] <= 7'b0000000;
end
default: Y <= 8'bxxxxxxxx;
endcase
end
endmodule

Simulation Results
verification phase

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