Data Memory block
Block diagram for Data Memory block
Figure.1 Block diagram of Data Memory Block
VERILOG code
module memory_block(
output reg [31:0] Read_data,
input MemWrite,
input MemRead,
input [31:0] Address,
input [31:0] Write_data
);
reg [7:0] mem_addr;//_read;
//reg [7:0] mem_addr_write;
reg [31:0] block[0:255];
initial
begin
block[19] <= 32'h55555555;
block[200] <= 32'hfedcba98;
end
always @(Address)
begin
mem_addr <= Address[7:0];
end
always @(mem_addr,MemWrite,MemRead)
begin
if(MemWrite == 1'b1 && MemRead == 1'b0)
begin
block[mem_addr] <= Write_data;
end
if(MemRead == 1'b1 && MemWrite == 1'b0)
begin
Read_data <= block[mem_addr];
end
end
endmodule
Theoretical Results
Inputs: 1. Mem_Write = 1’b1
Mem_Read = 1’b0
Address = 32’h00000000
Write_data = 32’h98fedcba
2. Mem_Write = 1’b0
Mem_Read = 1’b0
Address = 32’h00000000
Output: Read_data = 32’h98fedcba
Simulation Result of Data Memory block
Figure.2 Simulation results for Data Memory Block
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