Coding the decoder blocks |
I enlight these:
What are decoder's?
2to4 decoder
3to8 decoder
4to16 decoder
Applications of decoder unit
- What are decoder's?
A decoder is a circuit that changes a code into a set of signals. In general a decoder has N-inputs and 2^N (power(2,N))outputs. Decoders are simply a collection of logic gates which are arranged in a specific way so as to breakdown any combination of inputs to a set of terms that are all set to '0' apart from one term.
Internal Circuit of 2 to 4 decoder
logic's for 2 to 4 decoder |
Truth table of 2 to 4 decoder
functionality |
VHDL Coding
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoding is
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoding is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end decoding;
architecture Behavioral of decoding is
begin
process (a,en)
begin
if(en ='1') then
case a is
when "00" => y <= "0001";
when "01" => y <= "0010";
when "10" => y <= "0100";
when "11" => y <= "1000";
when others => y <= "0000";
end case;
else
y<= "0000";
end if;
end process;
end Behavioral;
Simulation Results
verification |
Verilog Coding
module decoding_2_4(
output reg [3:0] y,
input en,
input [1:0] a
);
always @(en or a)
begin
if(en==1'b1)
begin
case(a)
2'b00: y <= 4'b0001;
2'b01: y <= 4'b0010;
2'b10: y <= 4'b0100;
2'b11: y <= 4'b1000;
default: y <= 4'b0000;
endcase
end
else
y <= 4'b0000;
end
endmodule
Simulation Results
verification |
Truth table of 3 to 8 decoder
functionality
Verilog Coding
module decode_3to8(
output reg [7:0]y,
input [2:0]x,
input en
);
always @(x or en)
begin
if(en==1'b1)
begin
case(x)
3'b000: y <= 8'b00000001;
3'b001: y <= 8'b00000010;
3'b010: y <= 8'b00000100;
3'b011: y <= 8'b00001000;
3'b100: y <= 8'b00010000;
3'b101: y <= 8'b00100000;
3'b110: y <= 8'b01000000;
3'b111: y <= 8'b10000000;
default: y <= 8'b00000000;
endcase
end
else
begin
y <= 8'bz;
end
end
endmodule
Simulation Results
verification phase
VHDL Coding
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec_3_8 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7 downto 0));
end dec_3_8;
architecture Behavioral of dec_3_8 is
begin
process (a,en)
begin
if(en ='1') then
case a is
when "000" => y <= "00000001";
when "001" => y <= "00000010";
when "010" => y <= "00000100";
when "011" => y <= "00001000";
when "100" => y <= "00010000";
when "101" => y <= "00100000";
when "110" => y <= "01000000";
when "111" => y <= "10000000";
when others => y <= "00000000";
end case;
else
y<= "00000000";
end if;
end process;
end Behavioral;
Simulation Results
verification phase
- 4 to 16 decoder
IC block for 4 to 16 decoder from two 3 to 8 decoder's
using two 3 to 8 decoder blocks
Truth table of 4 to 16 decoder
functionality
VERILOG coding
module decode_4to16(
output [15:0] y,
input [3:0] x
);
decode_3to8 d1(.x(x[2:0]),.en(~x[3]),.y(y[7:0]));
decode_3to8 d2(.x(x[2:0]),.en(x[3]),.y(y[15:8]));
endmodule
/*
module decode_3to8(
output reg [7:0]y,
input [2:0]x,
input en
);
always @(x or en)
begin
if(en==1'b1)
begin
case(x)
3'b000: y <= 8'b00000001;
3'b001: y <= 8'b00000010;
3'b010: y <= 8'b00000100;
3'b011: y <= 8'b00001000;
3'b100: y <= 8'b00010000;
3'b101: y <= 8'b00100000;
3'b110: y <= 8'b01000000;
3'b111: y <= 8'b10000000;
default: y <= 8'b00000000;
endcase
end
else
begin
y <= 8'b00000000;
end
end
endmodule */
Simulation Results
verification
VHDL coding
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity for_4_16 is
Port ( y : out STD_LOGIC_VECTOR (15 downto 0);
x : in STD_LOGIC_VECTOR (3 downto 0));
end for_4_16;
--component is same as in the above 3 to 8 decoder program vhdl
architecture Behavioral of for_4_16 is
component dec_3_8
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7 downto 0));
end component;
begin
l1: dec_3_8 PORT MAP(x(2 downto 0),not x(3),y(7 downto 0));
l2: dec_3_8 PORT MAP(x(2 downto 0),x(3),y(15 downto 8));
end Behavioral;
Simulation Results
verification
- Applications of decoder unit
Used in ROM's(memory)Used in digital communications(demodulation)
Used in TV remotes
Used in computer keyboard
Used in Traffic lights control systems.
Used in LED array(display units). etc.,
functionality |
Verilog Coding
module decode_3to8(
output reg [7:0]y,
input [2:0]x,
input en
);
always @(x or en)
begin
if(en==1'b1)
begin
case(x)
3'b000: y <= 8'b00000001;
3'b001: y <= 8'b00000010;
3'b010: y <= 8'b00000100;
3'b011: y <= 8'b00001000;
3'b100: y <= 8'b00010000;
3'b101: y <= 8'b00100000;
3'b110: y <= 8'b01000000;
3'b111: y <= 8'b10000000;
default: y <= 8'b00000000;
endcase
end
else
begin
y <= 8'bz;
end
end
endmodule
Simulation Results
verification phase |
VHDL Coding
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec_3_8 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7 downto 0));
end dec_3_8;
architecture Behavioral of dec_3_8 is
begin
process (a,en)
begin
if(en ='1') then
case a is
when "000" => y <= "00000001";
when "001" => y <= "00000010";
when "010" => y <= "00000100";
when "011" => y <= "00001000";
when "100" => y <= "00010000";
when "101" => y <= "00100000";
when "110" => y <= "01000000";
when "111" => y <= "10000000";
when others => y <= "00000000";
end case;
else
y<= "00000000";
end if;
end process;
end Behavioral;
Simulation Results
verification phase |
- 4 to 16 decoder
IC block for 4 to 16 decoder from two 3 to 8 decoder's
Truth table of 4 to 16 decoder
using two 3 to 8 decoder blocks |
Truth table of 4 to 16 decoder
functionality |
VERILOG coding
module decode_4to16(
output [15:0] y,
input [3:0] x
);
decode_3to8 d1(.x(x[2:0]),.en(~x[3]),.y(y[7:0]));
decode_3to8 d2(.x(x[2:0]),.en(x[3]),.y(y[15:8]));
endmodule
/*
module decode_3to8(
output reg [7:0]y,
input [2:0]x,
input en
);
always @(x or en)
begin
if(en==1'b1)
begin
case(x)
3'b000: y <= 8'b00000001;
3'b001: y <= 8'b00000010;
3'b010: y <= 8'b00000100;
3'b011: y <= 8'b00001000;
3'b100: y <= 8'b00010000;
3'b101: y <= 8'b00100000;
3'b110: y <= 8'b01000000;
3'b111: y <= 8'b10000000;
default: y <= 8'b00000000;
endcase
end
else
begin
y <= 8'b00000000;
end
end
endmodule */
Simulation Resultsverification |
VHDL coding
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity for_4_16 is
Port ( y : out STD_LOGIC_VECTOR (15 downto 0);
x : in STD_LOGIC_VECTOR (3 downto 0));
end for_4_16;
--component is same as in the above 3 to 8 decoder program vhdl
architecture Behavioral of for_4_16 is
component dec_3_8
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7 downto 0));
end component;
begin
l1: dec_3_8 PORT MAP(x(2 downto 0),not x(3),y(7 downto 0));
l2: dec_3_8 PORT MAP(x(2 downto 0),x(3),y(15 downto 8));
end Behavioral;
Simulation Results
verification |
- Applications of decoder unit
Used in TV remotes
Used in computer keyboard
Used in Traffic lights control systems.
Used in LED array(display units). etc.,
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