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| Multiplexer's |
- MULTIPLEXER's
General IC block
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| General MUX |
A multiplexer (or mux) is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select
which input line to send to the output. Multiplexers
are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data selector. An electronic multiplexer makes it possible for
several signals to share one device or resource, for example one A/D converter or one communication line, instead of
having one device per input signal.
- 2 to 1 Multiplexer
IC block
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| IC for 2to1 Mux |
Internal Logic
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| logic's : A - D0, B - D1, X - S |
Truth Table
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| functionality |
VHDL Code
entity mux_2_to_1 is
Port ( Y : out STD_LOGIC;
D : in STD_LOGIC_VECTOR (1 downto 0);
S : in STD_LOGIC;
E : in STD_LOGIC);
end mux_2_to_1;
architecture Behavioral of mux_2_to_1 is
begin
process(D,S,E)
begin
if(E = '1') then
if(S = '0') then
Y <= D(0);
elsif(S = '1') then
Y <= D(1);
else
Y <= 'X';
end if;
else
Y <= 'X';
end if;
end process;
end Behavioral;
VERILOG Code
module mux_2_1(
output reg Y,
input [1:0] D,
input S,
input E
);
always @(D,S,E)
begin
if(E == 1'b1)
begin
if(S == 1'b0)
Y <= D[0];
else if(S == 1'b1)
Y <= D[1];
else
Y <= 1'bx;
end
else
Y <= 1'bx;
end
endmodule
Simulation Results
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| Logic's Verification with 2-bit data "10" |
- 4 to 1 Multiplexer
IC Block
 |
| IC for 4 to 1 MUX |
Internal Logic
 |
| Logic's |
Truth Table
 |
| logical Table |
entity mux_4to1 is
port( D : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic);
end mux_4to1;
architecture functional of mux_4to1 is
begin
process (S,D)
begin
case S is
when "00" => Y <= D(0);
when "01" => Y <= D(1);
when "10" => Y <= D(2);
when "11" => Y <= D(3);
when others => Y <= 'X';
end case;
end process;
end functional;
VERILOG Code
module mux_4_1(
output reg Y,
input [1:0] S,
input [3:0] D
);
always @(S,D)
begin
case(S)
2'b00: Y <= D[0];
2'b01: Y <= D[1];
2'b10: Y <= D[2];
2'b11: Y <= D[3];
default: Y <= 1'bx;
endcase
end
endmodule
Simulation Results
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| Verification Phase |
- 8 to 1 Multiplexer
IC Block
 |
| IC Configuration |
Internal Logic
 |
| logical description |
Truth Table
 |
| functionality |
VHDL Code
entity
mux_8to1 is
port(
D : in std_logic_vector(7 downto 0);
S
: in std_logic_vector(2 downto 0); Y : out std_logic);
end
mux_8to1;
architecture
functional of mux_8to1 is
begin
process
(S,D)
begin
case
S is
when
"000" => Y <= D(0);
when
"001" => Y <= D(1);
when
"010" => Y <= D(2);
when
"011" => Y <= D(3);
when
"100" => Y <= D(4);
when
"101" => Y <= D(5);
when
"110" => Y <= D(6);
when
"111" => Y <= D(7);
when
others => Y <= 'X';
end
case;
end
process;
end
functional;
VERILOG Code
module mux_8_1(
outputreg Y,
input [2:0] S,
input [7:0] D
);
always @(S,D)
begin
case(S)
3'b000: Y <= D[0];
3'b001: Y <= D[1];
3'b010: Y <= D[2];
3'b011: Y <= D[3];
3'b100: Y <= D[4];
3'b101: Y <= D[5];
3'b110: Y <= D[6];
3'b111: Y <= D[7];
default: Y <= 1'bx;
endcase
end
Simulation Results
 |
| verification phase |
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