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AND gate logic

AND gate logic

Block diagram of AND gate logic

Figure.1 Block diagram for AND gate logic

VERILOG Code

module anding_logic(

output reg a,

input branch,

input zero

);

always @(branch,zero)

begin

a <= branch & zero;

end

endmodule

Theoretical Results

When both inputs are high then output is high

Simulation Result for AND gate logic

Figure.2 Simulation result for AND gate logic

CONVERSATION