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| JK FF title |
The Flip-flops are the basic memory (sequential) elements used in the ASIC/SOC designs. These flipflops can store 1'bit data. Latches are level-sensitive & Flipflop's are clock edge triggered. A Flipflop is a latch with an additional edge detection circuit. Flipflops provide better observability & controlability during events. Though Flip-flops consume more power when compared to latches, many designers still prefer Flip-flops.
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| JK block |
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| Truth Table for JK FF |
JK flipflop Verilog Code:
module JK_ff_Phase_detector(Q, Q_bar, CLK, CLR, J, K);
input J, K, CLK, CLR;
output Q, Q_bar;
reg Q;
assign Q_bar = ~Q;
always @(posedge CLK or posedge CLR)
begin
if (CLR == 1)
begin
Q <= 0;
end
else
begin
Q <= (J & (~K)) | ((~J)&(~K)&Q) | (J & K & (~Q));
end
end
endmodule
synthesized schematic:
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| JK top |
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| internal |
Waveform simulation:
testbench:
module test_module(
);
reg J;
reg K;
reg CLK;
reg CLR;
initial CLK = 1'b0;
always #25 CLK = ~CLK;
JK_ff_Phase_detector JK0( .Q(Q), .Q_bar(Q_bar), .CLK(CLK), .CLR(CLR), .J(J), .K(K) );
initial begin
J <= 0;
K <= 0;
CLR <= 0;
#20 J <= 0;
K <= 1;
CLR <= 0;
#50 J <= 1;
K <= 0;
CLR <= 0;
#80 J <= 1;
K <= 1;
CLR <= 0;
#110 J <= 1;
K <= 1;
CLR <= 1;
#100 $finish;
end
initial
$monitor ("J=%0d K=%0d CLR=%0d Q=%0d", J, K, CLR, Q);
endmodule
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| waveforms |
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| console |
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