ALU Control Unit
Block diagram of ALU control Unit
Figure.1 Block diagram of ALU Control Unit
VERILOG Code
module ALU_control_signals(
output reg [2:0] Op_select,
input [5:0] Instruction,
input [1:0] ALUOp
);
always @(ALUOp)
begin
Op_select[0] <= (ALUOp[1] & (Instruction[3] | Instruction[0]));
Op_select[1] <= (~ALUOp[1])|(~Instruction[2]);
Op_select[2] <= ALUOp[0] | (ALUOp[1] & Instruction[1]);
end
endmodule
Theoretical Results
Inputs :ALUOp = 2’b00
Instruction[5:0] = 6’b101010
Outputs : ALU = 3’b010 (add)
Simulation Result for ALU control Unit
Figure.2 Simulation Result for ALU Control Unit
0 comments:
Post a Comment