The Multipliers are used in various applications like DSP applications, Graphical Video processing, in core units(arithmetical) of processors etc., The Column compression Multipliers have gained popularity because of their High-computational speed. Wallace and Dadda Multipliers are the well renowned Column compression Multipliers. The Wallace Multiplier was proposed by Chris Wallace, a Australian computer scientist in 1964. The Dadda Multiplier was proposed by Luigi Dadda, an Italian computer Engineer by altering the Wallace Multiplier. Both these Wallace and Dadda Multipliers are reduction based. The reduction is achieved by compressing the columns with a (3,2) counter (Full adder) and a 

(2,2) counter (Half adder). 

In this(here), we have focused on 8bit Wallace Multiplier. 

input a = a[7:0] -> 8bit bus

input b = b[7:0] ->  8bit bus

operation = a X b = 8bit  X  8bit

resultant = a X b = r = r[15:0] -> 16 bit result

Step 1 :  We obtain the partial products by doing "and" logic operation. The partial products are represented as . dot in below image.  pp (partial products) = (a[i] & b[j]) , where i,j = 0,1,2,...7

Step4 : reduction from 6row to 4row.

Step6: final reduction 3 to 2 & using ripple carry adder obtaining the result 16bit

The verilog code is developed for a 8bit wallace multiplier & implemented.

The basic modules used in construction of the 8bit muliplier are (2,2) compressor - a Half Adder & (3,2) compressor - Full Adder.

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