Fixed 1-bit Adder Block (Increments the
Instruction)
Block diagram of fixed 1-bit Adder block
Figure.1 Block diagram
of fixed 1-bit adder block
VERILOG Code
module adder_04(
output reg [31:0] Y,
input [31:0] X
);
always @(X)
begin
Y <= X+32'h00000001;
end
endmodule
Theoretical results
Input X
<= 32'h84155641
Output Y
<= 32’h84155642
Simulation Result for fixed 1-bit Adder block
Figure.2 Simulation
Result for fixed 1-bit adder block
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