Mux 2 to 1_32 bit
Block diagram of MUX-32 bit
Figure.1 Block diagram of MUX-32 bit
VERILOG Code
module mux_2_to_1_32_bit(
output reg [31:0] z,
input [31:0] x,
input [31:0] y,
input s,
input clock
);
always @(s)
begin
if(s==1'b1)
z<=x;
else if(s==1'b0)
z<=y;
else
z<=32'hxxxxxxxx;
end
endmodule
Theoretical Results
Inputs: X = 32’d17
Y = 32’d18
S = 1’b1
Output : Z = 32’d17
Simulation Result for MUX-32 bit
Figure.2 Simulation result for MUX-32 bit
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