ALU unit
Block diagram of ALU Unit
Figure.1 Block diagram of ALU Unit
VERILOG code
module alu(
output reg [31:0] r,
input clock,
input [31:0] x,
input [31:0] y,
input [2:0] op,
output reg zero
//output reg Overflow
);
always @(op)
begin
case(op)
3'b000: r <= x&y;
3'b001: r <= x|y;
3'b010: r <= x+y;
3'b011: r <= 0;
3'b100: r <= 0;
3'b101: r <= 0;
3'b110: r <= x-y;
3'b111: r <= x-y;
default: r <= 32'hxxxxxxxx;
endcase
end
always @(/*posedge clock*/r)
begin
if(r == 32'h00000000)
zero <= 1'b1;
else if(r == 32'hxxxxxxxx)
zero <= 1'bx;
else
zero <= 1'b0;
end
endmodule
Theoretical Results
Inputs : x <= 32’habcdef98
Y <=32’habcdef98
Op <= 010(add)
Outputs: r <= 32’h579bdf30
Zero <= 1’b0
Simulation Result for ALU Unit
Figure.2 Simulation Result for ALU Unit
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