image1 image2 image3

HELLO I'M LiNuS|WELCOME TO MY PERSONAL BLOG|I LOVE TO DO CREATIVE THINGS|I PRESENT MY WORKS ON VLSI AND EMBEDDED

PC Register

PC Register


Block diagram of PC register
Figure.1 Block diagram of PC Register



VERILOG Code

module pc_register(
    output reg [31:0] y,
    input [31:0] x,
    input clock
    );
reg [31:0] s;

initial 
begin
s <= 32'h00000000;
end

always @(posedge clock)
begin
y <= s;
end

always @(x)
begin
s <= x;
end
endmodule



Theoretical Results
             Inputs: clock with period 1000ns
                          X = next address to be executed
            Output: Y = present address of Instruction being executed



Simulation Result for PC register


Figure.2 Simulation Result for PC Register


Share this:

CONVERSATION

0 comments:

Post a Comment