Traffic Lights FSM

FSM :
                                           The FSM is the Finite State Machine, this is mainly intended for the design of sequential circuits. The Sequential circuits are in general the Combinational circuits with some memory elements in it. In real life to encounter the storage and processing of data we prefer the sequential ones. These circuits keep track of the states to be occurred. The Sequential design is carried out by building the state diagram at first. The state diagram describes the functional nature and switching behavior of the system. The Sequential design can be synchronous or asynchronous in nature. If its synchronous then the states decides the output. If its asynchronous then output can change with the input also. The State diagram is developed based on the requirement. There are two types of machines possible with sequential circuits i.e, one is moore machine whose outputs are dependent only on states where as the other mealey machine's output dependent on current state as well as inputs. By the help of state diagram we develop the state table and then with the help of excitation table of the required flipflops we develop the current state logic's which are function of previous state and inputs. 



TRAFFIC LIGHT FSM :
                                    A Traffic light has 3 states. They are Red, Green and Yellow. 

FSM of traffic lights

VHDL CODE:(by adjusting timer variable to set the delay in each states)


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity TRAFFIC_LIGHTS is
    Port ( clock : in  STD_LOGIC;
           r : out  STD_LOGIC;
           g : out  STD_LOGIC;
           y : out  STD_LOGIC);
end TRAFFIC_LIGHTS;



architecture Behavioral of TRAFFIC_LIGHTS is

begin

        process(clock)

             variable state: bit_vector(1 downto 0) := "00";
             variable timer: integer := 0;

              begin

                if(clock'event and clock = '1') then

                   case state is

                      when "00" => 

                         if(timer < 2) then

                                         g <= '0';
                                         r <= '0';
                                         y <= '1';

                                        timer := timer + 1;
                                        state := state;

                        else

                                         state := "01";
                                         timer := 0;
                       end if;

                    when "01" => 

                       if(timer < 5) then

                                         g <= '0';
                                         r <= '1';
                                         y <= '0';

                                         timer := timer + 1;
                                         state := state;

                      else
                                         timer := 0;
                                         state := "10";
                      end if;
                   when "10" =>

                        if(timer < 4) then
                                           g <= '1';
                                           r <= '0';
                                           y <= '0';

                                           timer := timer + 1;
                                           state := state;

                        else
                                           timer := 0;
                                           state := "00";
                        end if;
                    when others => state := "10";
                                           timer := 0;

                    end case;
               else
                    state := state;

        end if;

    end process;


end Behavioral;





VERILOG CODE: (by adjusting timer variable to set the delay in each states) 

module traffic_lights_control_unit(
    output reg r,
    output reg g,
    output reg y,
    input clock
    );
parameter red = 0;
parameter green = 1;
parameter yellow = 2;

reg [1:0]PS;
reg [1:0]NS;
reg [2:0]timer;

always @(posedge clock)
begin
   case(PS)
      red: 
begin 
if(timer < 3'b101)
begin
timer = timer + 1;
NS <= PS;
end
else
begin
NS <= green;
timer = 0;
end
end
   green: 
begin
if(timer < 3'b100)
begin
timer = timer + 1;
NS <= PS;
end
else
begin
NS <= yellow;
timer = 0;
end
end
  yellow: 
begin
if(timer < 3'b011)
begin
timer = timer + 1;
NS <= PS;
end
else
begin
NS <= red;
timer = 0;
end
end
   default: NS <= red;
 endcase

end



always @(NS)
begin
           PS <= NS;
end

always @(*)
begin
      case(PS)
              red: begin
                            r <= 1'b1;
                            g <= 1'b0;
                            y <= 1'b0;
                      end

             green: begin
                            r <= 1'b0;
                            g <= 1'b1;
                            y <= 1'b0;
                         end

             yellow: begin
                          r <= 1'b0;
                          g <= 1'b0;
                          y <= 1'b1;
                          end
      endcase
end


endmodule