The Customer Requirements for an IC chip can vary based on its real-time usage/application/operational conditions. IC chips has evolved from SSI -> MSI -> LSI -> VLSI -> ULSI in few decades, accommodating gates from 10’s to Millions & billions over few decades. The EDA Tools have come into picture from various vendors to serve the huge count design needs. In Today’s World, the Micro chips are used in various  areas like Personal computing, Cloud storage, Cloud computing, Networking, Gaming, Artificial Intelligence, Machine learning, Autonomous, Defence, Aerospace, Medical Screening, R&D, Marketing, Trading, Agricultural advancements etc., Based on the customer requirements, the system specifications are drawn. The system specifications include the operating speed, arithmetic/logic operations capability, data bus width, functional units & their interfaces to external communication. The architecture is a block diagram describing all the operational units specifying the actual data flow in the required clock cycles. Architectural design is documented for every IC chip to maintain the versions & to convey the data operations, data flow & data interfaces information to Logic/RTL designer’s team. The Logic designer’s make use of the architectural design information to develop the behavioural description model. The behavioural description model is written using the HDL’s. The HDL is the Hardware description language and some of those are vhdl (VHSIC HDL), Verilog & system Verilog HDL’s. The HDL’s allow the designers to describe the logic behaviour in various flow modelling – concurrent (data flow), Behavioural, Structural, Mixed-flow & Gate-level modelling. The behavioural description model is written using the Verilog HDL constructs like always, initial, begin, end etc., to loop the data capture/operations at required clock cycles. The Behavioural description model is process & technology independent. This model can be re-used for other process & technology node. The RTL model is the Register transfer Level which contains the data flow through registers (sequential elements). Behavioural description model is translated to RTL model using EDA tools. After developing the RTL code, the functional verification (simulation) is carried with input waveform combinations to predict the output desired waveforms using the simulation tools available.

The RTL code post-verification is consumed for logic synthesis. The logic synthesis is the process of obtaining a gate-level netlist (structural netlist) from the given RTL. Synthesis tools perform the translation of RTL (in HDL) to tool specific gates. The translated tool specific gates are then mapped to the targeted process & technology specific gates of std cell library. Later, translation & mapping, the optimization is carried on the design to achieve better performance in terms of timing/area/power. Post synthesis the formal verification is carried to check the RTL to obtained gate-level netlist for logical equivalency. The formal verification tools based on the mathematical algorithms that builds logical cones to prove logical equivalency between RTL to gate-level netlist. The Floorplan is the placement of hard macros (comes from external IP team/owner), ports (external interface) & tracks/boundary of block initialization. The power planning is carried along with floorplan to deliver the power to std cell rails (follow pins) from the Top power stripes that hook to the external power rings.  The placement is carried post floorplan for placing the soft logic physically to obtain better control in area/power/timing/congestion. The soft logic is the collection of standard cell gates which are flexible to undergo optimizations. The hard logic is the collection of hard macros which can be digital IP or analog IP that can’t undergo any optimization at back-end. Post placement, CTS is the clock tree synthesis that builds the physical clock to all the sequential in the design. The two aspects that are focused here is Clock Skew & Clock latency (insertion delay). The Route builds the physical paths with metal layers for all the signal connections other than clock. Post-route the STA (static timing analysis) is carried to perform setup/hold synchronous timing checks & recovery/removal asynchronous checks. The Formal Verification will once again be carried post-route to ensure logic equivalency. The Main stages of APR/PnR flow are Place, CTS & Route. At these 3 stages, optimization is carried out to attain better performance in terms of power/area/timing. The optimizations are cell up/downsizing, logical restructuring, buffering to split fanout, cloning to balance load, routing in higher layers/widths, shielding for crosstalk reduction, legalization of cells etc., The ECO implementation include the minor changes in design followed by selective routing to improve the timing/area/power. DRC/layout verification is carried out to rectify the design aspects and loop any feedback to APR/PnR level. DRC’s are the design rule checks from the fab (PDK) to obtain better manufacturing yields. The fabrication of the IC chip is the crucial step that lets the physical IC tape out for real time usage. Fabrication is the most costliest process that happens chemically by growing the CMOS/FINFET transistor by doping n or p type impurities on the silicon wafer. The layout (either GDSII or OASIS) is the input for the fab.  After fabrication the post-silicon validation is carried out to detect the manufacturing defects such as electrical faults using the pre-existing scan chains (DFT) & functional defects using test patterns & software OS booting & thermal operating conditions etc., This validation process is little time consuming and it is the last stage to capture all the defects for Re-Spin/bulk volume production of IC chip. Re-Spin is going back to VLSI flow to rectify the faults either in RTL or APR/Pnr. The Bulk volume production is to get IC chips in huge quantity for marketing/delivering to customers.