Top module implementation of RISC 32-bit processor
BLOCK
 |
| top module |
VERIOG Code
module Top_module_for_RISC_single_cycle_32_bit(
input clock,
input Reset
);
wire ALUSrc,RegDst,RegWrite,MemtoReg,MemWrite,MemRead,branch,jump,zero;
wire [1:0] ALUOp;
wire [31:0] Instruction,Address;
wire [2:0] op;
wire [31:0] PC_4,ALUSrc_1,r,Read_data,adding_1,jump_input_0;
wire [31:0] read_reg_1,read_reg_2,write_data,adding_r,jump_address;
wire [31:0] ALU_input_2;
wire [4:0] write_reg;
wire a5;
wire [27:0] x;
adder_04 a4(
.Y(PC_4),
.X(Address)
);
pc_register p1(
.y(Address),
.x(jump_address),
.clock(clock)
);
instr_memory_unit i0(
.Instruction(Instruction),
.Address(Address)
);
Single_cycle_Control_unit_FSM s0(
.ALUSrc(ALUSrc),
.RegDst(RegDst),
.RegWrite(RegWrite),
.MemtoReg(MemtoReg),
.ALUOp(ALUOp),
.MemWrite(MemWrite),
.MemRead(MemRead),
.branch(branch),
.jump(jump),
.Opcode(Instruction[31:26]),
.zero(),
.Overflow(),
.Reset(Reset),
.clock(clock)
);
ALU_control_signals a0(
.Op_select(op),
.Instruction(Instruction[5:0]),
.ALUOp(ALUOp)
);
alu a1(
.r(r),
.clock(clock),
.x(read_reg_1),
.y(ALU_input_2),
.op(op),
.zero(zero)
//output reg Overflow
);
Register_file r1(
.reg_1_data(read_reg_1),
.reg_2_data(read_reg_2),
.read_reg_1(Instruction[25:21]),
.read_reg_2(Instruction[20:16]),
.write_reg(write_reg),
.write_data(write_data),
.RegWrite(RegWrite),
.clock(clock)
);
memory_block m1(
.Read_data(Read_data),
.MemWrite(MemWrite),
.MemRead(MemRead),
.Address(r),
.Write_data(read_reg_2)
);
shifting_left s1(
.Y(adding_1),
.X(ALUSrc_1)/*,
.clock(clock)*/
);
shit_left_2_in_J_type s2(
.Y(x),
.X(Instruction[25:0])/*,
.clock(clock)*/
);
sign_extend s3(
.y(ALUSrc_1),
.x(Instruction[15:0])/*,
.clock(clock)*/
);
mux_2_to_1_5_bit m2(
.z(write_reg),
.x(Instruction[15:11]),
.y(Instruction[20:16]),
.RegDst(RegDst)
);
adding_block a3(
.r(adding_r),
.y(PC_4),
.x(adding_1)
);
mux_2_to_1_32_bit m3(
.z(ALU_input_2),
.x(ALUSrc_1),
.y(read_reg_2),
.s(ALUSrc),
.clock(clock)
);
mux_2_to_1_32_bit m4(
.z(write_data),
.x(Read_data),
.y(r),
.s(MemtoReg),
.clock(clock)
);
anding_logic a6(.a(a5),.branch(branch),.zero(zero));
//assign a5 = branch & zero;
mux_2_to_1_32_bit_clocked m5(
.z(jump_input_0),
.x(adding_r),
.y(PC_4),
.s(a5)
);
mux_2_to_1_32_bit_clocked m6(
.z(jump_address),
.x({PC_4[31:28],x[27:0]}),
.y(jump_input_0),
.s(jump)
);
endmodule
Theoretical Results
1. R-type Instruction Execution
Inputs: clock with period 1000ns
1.1 During cycle 1
Instruction is fetch from the Instruction memory by the address pointed by pc_register
Address = 32’b00000000000000000000000000000000
Instruction = 32’b00000000000000000000100000100000
Instruction is decoded in the same cycle
PC_4 = 32’b00000000000000000000000000000001
Registers are read
Read_reg_1 = 32’b00000000000000000000100101000110
Read_reg_2 = 32’b00000000000000000000100101000110
1.2 During cycle 2
ALU performs operation based on control signals
Control unit output logic
ALUSrc = 1’b1
ALUOp = 2’b10
Op = 3’b010(add)(from alu control unit)
ALU unit performs addition on the data read in the cycle 1 from registers
Result r = 32’b00000000000000000001001010001100
1.3 During cycle 3
The result from ALU unit is written back to the register file
The control unit logics are
RegDst = 1'b1
jump = 1'b0
ALUSrc = 1'b0
MemtoReg = 1'b0
RegWrite = 1'b1
MemRead = 1'b0
MemWrite = 1'b0
branch = 1'b0
ALUOp = 2'b10
Register write address = 5’b00001
Write_data = 32’b00000000000000000001001010001100
1.2 Simulation Results
1.2.1 Part 1
Figure.1 Simulation result for Top module implementation of 32 bit RISC processor part 1
1.2.2 Part 2
Figure5.32 Simulation result for Top module implementation of 32 bit RISC processor part 2
Conclusion
With the rapid development of silicon technology RISC includes extensions to RISC concepts that help achieve given levels of performance at significantly lower cost than other systems. The main features of RISC processor are the instruction set can be hardwired to speed instruction execution. In the present work, the design of a 32-bit data width Reduced Instruction Set Computer (RISC) processor is presented. It has a complete instruction set, program and data memories, general purpose registers and a simple Arithmetical Logical Unit (ALU) for basic operations. In this design, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory.
The 32-bit RISC processor with 5 instruction set has been designed. The Load word instruction is executed in 4cycles, R-type and Store word instruction is executed in 3cycles and Branch and Jump instructions are executed in 2cycles. This processor can be used as a systolic core to perform mathematical computations like solving polynomial and differential equations. Apart from this it can be used in portable gaming kits.
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