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ENCODER's

ENCODER

  • What are Encoders?
General Block Diagram of Encoder
                                   The digital encoders produce outputs of 2-bit, 3-bit or 4-bit etc., codes depending upon the number of data input lines.  An n-bit binary encoder has  2 input lines and n-bit output lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations. The output lines of a digital encoder generate the binary equivalent of the input line whose value is equal to 1 and are available to encode either a decimal or hexadecimal input pattern to typically a binary or B.C.D (binary coded decimal) output code. One of the main disadvantages of standard digital encoders is that they can generate the wrong output code when there is more than one input present at logic level 1. One simple way to overcome this problem is to Prioritise the level of each input pin and if there was more than one input at logic level 1 the actual output code would only correspond to the input with the highest designated priority. Then this type of digital encoder is known commonly as a Priority Encoder.

  • 4 by 2 Encoder
IC block
IC block

Truth Table
Truth table

VHDL Code
entity encoder is
  port(
         D : in STD_LOGIC_VECTOR(3 downto 0);
         Q : out STD_LOGIC_VECTOR(1 downto 0)
         );
end encoder;

architecture Behavioral of encoder is

begin
    process(D) is
    begin
        case D is
            when "0001" => Q <= "00";
            when "0010" => Q <= "01";
            when "0100" => Q <= "10";
            when "1000" => Q <= "11";
            when others => Q <= "ZZ";
        end case;
    end process;
end Behavioral;


Verilog code
module encoder(
    output reg [1:0] Q,
    input [3:0] D
    );

always @(D)
begin
case(D)
4'b0001: Q <= 2'b00;
4'b0010: Q <= 2'b01;
4'b0100: Q <= 2'b10;
4'b1000: Q <= 2'b11;
default: Q <= 2'bzz;
endcase
end
endmodule


Simulation Results
Simulation Results


  • 8by3 Encoder
IC Block
8by3 Encoder

LOGIC DIAGRAM
LOGIC's

Truth Table
Truth table

VHDL Code

entity encoder is
  port(
         D : in STD_LOGIC_VECTOR(7 downto 0);
         Q : out STD_LOGIC_VECTOR(2 downto 0)
         );
end encoder;

architecture Behavioral of encoder is

begin
    process(D) is
    begin
        case D is
            when "00000001" => Q <= "000";
            when "00000010" => Q <= "001";
            when "00000100" => Q <= "010";
            when "00001000" => Q <= "011";
            when "00010000" => Q <= "100";
            when "00100000" => Q <= "101";
            when "01000000" => Q <= "110";
            when "10000000" => Q <= "111";
            when others => Q <= "ZZZ";
        end case;
    end process;
end Behavioral;



Verilog Code

module enc(
    output reg [2:0] Q,
    input [7:0] D
    );

always @(D)
begin
case(D)
8'b00000001: Q <= 3'b000;
8'b00000010: Q <= 3'b001;
8'b00000100: Q <= 3'b010;
8'b00001000: Q <= 3'b011;
8'b00010000: Q <= 3'b100;
8'b00100000: Q <= 3'b101;
8'b01000000: Q <= 3'b110;
8'b10000000: Q <= 3'b111;
default: Q <= 3'bzzz;
endcase
end
endmodule

Simulation Results
verification phase
  • Priority Encoder
                                                 priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the original number starting from zero of the most significant input bit. They are often used to control interrupt requests by acting on the highest priority encoder. If two or more inputs are given at the same time, the input having the highest priority will take precedence.

IC Block
IC for 8by3 priority Encoder

TRUTH TABLE
Truth table
VHDL Code

entity encoder is

  port(
         D : in STD_LOGIC_VECTOR(7 downto 0);
         Q : out STD_LOGIC_VECTOR(2 downto 0)
         );
end encoder;

architecture Behavioral of encoder is

begin
process (D) is
begin
if(D(7) = '1') then
Q <= "111";
elsif(D(6) = '1') then
Q <= "110";
elsif(D(5) = '1') then
Q <= "101";
elsif(D(4) = '1') then
Q <= "100";
elsif(D(3) = '1') then 
Q <= "011";
elsif(D(2) = '1') then 
Q <= "010";
elsif(D(1) = '1') then
Q <= "001";
elsif(D(0) = '1') then
Q <= "000";
else 
Q <= "ZZZ";
end if;
end process;
end Behavioral;

VERILOG Code

module enc(

    output reg [2:0] Q,
    input [7:0] D
    );

always @(D)
begin
if(D[7] == 1'b1)
Q <= 3'b111;
else if(D[6] == 1'b1)
Q <= 3'b110;
else if(D[5] == 1'b1)
Q <= 3'b101;
else if(D[4] == 1'b1)
Q <= 3'b100;
else if(D[3] == 1'b1)
Q <= 3'b011;
else if(D[2] == 1'b1)
Q <= 3'b010;
else if(D[1] == 1'b1)
Q <= 3'b001;
else if(D[0] == 1'b1)
Q <= 3'b000;
else 
Q <= 3'bzzz;
end
endmodule

Simulation Results
verification


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