Register file
Block diagram of Register file
Figure.1 Block diagram of ALU Unit
VERILOG CODE
module Register_file(
output reg [31:0] reg_1_data,
output reg [31:0] reg_2_data,
input [4:0] read_reg_1,
input [4:0] read_reg_2,
input [4:0] write_reg,
input [31:0] write_data,
input RegWrite,
input clock
);
reg [31:0]registers[0:31];
initial
begin
registers[0] <= 32'd2374;
registers[3] <= 32'd12;
registers[8] <= 32'd24;
registers[9] <= 32'hfedcba98;
registers[17] <= 32'h00000001;
registers[18] <= 32'h00000001;
end
//reading_registers
always @(read_reg_1 or read_reg_2)
begin
reg_1_data <= registers[read_reg_1];
reg_2_data <= registers[read_reg_2];
end
//writing_registers
always @(posedge clock/*RegWrite*/)
begin
if(RegWrite == 1'b1)
begin
registers[write_reg] <= write_data;
end
end
endmodule
Theoretical Results
Inputs: read_reg_1 = 5’b00000
read_reg_2 = 5’b00011
Outputs : Read_data_1 = 32’d2374
Read_data_2 = 32’d12
Simulation Result for Register file
Figure.2 Simulation Results for ALU unit
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