Mux 2 to 1_5 bit
Block diagram of MUX-5 bit
Figure.1 Block diagram of MUX
VERILOG Code
module mux_2_to_1_5_bit(
output reg [4:0] z,
input [4:0] x,
input [4:0] y,
input RegDst
);
always @(RegDst)
begin
if(RegDst == 1'b1)
z <= x;
else if(RegDst == 1'b0)
z <= y;
else
z <= 5'bxxxxx;
end
endmodule
Theoretical Results
Inputs: A = 5’b11000
B = 5’b00111
So = 1
Ouput: Z = 5’b11000
Simulation Result for MUX-5 bit
Figure.2 Simulation Result for MUX-5 bit
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