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| MIPS Instruction set |
Introduction to MIPS
MIPS can be abbreviated as
Microprocessor without Interlocked Pipelining Stages. It was first developed by
Sony, Nintendo and NEC. This was developed to overcome the problems of the
conventional design i.e., using same instruction set for all the applications
makes instruction set busy and system the delaying system. Hence MIPS is made
as an alternative to conventional RISC Processor.
MIPS processor design is based on the
RISC design principle that emphasizes on a load/store architecture. Due to the
difference in time taken to access a register as compared to a memory location,
it is much faster to perform operations in on chip registers rather than in
memory. To eliminate the latency of memory operations, MIPS processor uses the
load/store architecture where the access to memory is only through load and
store instructions. The processor has many registers and operations are
performed in data present in those registers. The basic architecture of a MIPS
processor is shown in Figure.1
Figure.1 Top
level Structure of MIPS
When talking about the characteristics
of MIPS processors, it is very important to differentiate between the terms architecture
and hardware implementation. Architecture refers to the instruction set,
registers, address layouts etc. while hardware implementation refers to the
manner in which different processors use the architecture to build their own
model. The architecture remains the same for all MIPS based processors while
the implementations may differ. Different models like single cycle, multi-cycle
and pipelined designs have been used for designing the same. The pipelining can
further be implemented as a Parallel pipeline, Super pipeline or as a
Superscalar pipeline.
Lot of literature is available on
MIPS processor design. The explanation has detailed the hardware implementation
of a single cycle based design. Modifications have been introduced in the data path
to reduce dynamic power dissipation. We have talked about reducing power during
pipeline stalls. During these stall periods, NOPs are introduced which do not
do useful work but power may be dissipated if data transitions take place. For
power reduction, they have proposed to feed-back the previous data to the
pipeline during these periods and prevent toggling of data, thus reducing
dynamic power dissipation. This method does achieve power reduction but only
during pipeline stall stages, which may or may not occur frequently depending
on the compiler efficiency. In our design power reduction is achieved through
by-passing pipeline stages that cause unnecessary switching activity.
Instruction Set of
MIPS
The
Instruction Set of MIPS is divided for three different types of instructions
separately.
1. Register Type (R-Type)
2. Immediate
Type (I-Type)
3. Jump Type (J-Type)
Register Type
This instruction type is used for all the arithmetic
operations of the circuit. The instruction set representation of R-Type is
shown below:
Figure.2 Instruction
Set of R-Type Instruction
OP-Code is the 6-bit code which
defines the operational code which notifies other unit to perform its work.
Reg_s is a 5-bit source register
for which computation is carried out. In short the address if the source instruction can be stored here.
Reg_t is a 5-bit target source /
destination register used for computation. When multiple computations are to be
done then this register can be used. Execution of Op-code functions can be done
with this register.
Reg _d is an 5-bit destination
register used for storing the address where the instruction needs to be stored.
After the computation is done value is stored in the destination register.
Shift Amount is a 5-bit register
which specifies the value by which the data needs to be shifted. This register
saves the additional computation which needs to be done for shifting.
Function block notifies the ALU
which instruction to be executed. It also specifies functions with primary
opcode.
Instructions used by this type of
Instruction Set are addition (add), subtraction (sub) and other arithmetic
calculations.
Immediate Type
Figure.3 Instruction
Set of I-Type of Instruction
OP-Code is the 6-bit code which
defines the operational code which notifies other unit to perform its work.
Reg_s is a 5-bit source register
for which computation is carried out. In short the address if the source
instruction can be stored here.
Reg_t is an
5-bit target source / destination
register used for computation. When multiple computations are to be done
then this register can be used. Execution of Op-code functions can be done with
this register.
Immediate Address is an 16-bit
address gives the offset address added to the regular address. This 16-bit
immediate address is given to sign – extend unit to convert into 32- bit
value.
Jump Type
Figure.4 Instruction
Set of J-Type Instruction
OP-Code is the 6-bit code which defines the operational code
which notifies other unit to perform its work. Target Address is the address
where the instruction which is jumped to save.
The
layout of the instruction is called the instruction
format. As you can see from counting the number of bits, this MIPS
instruction takes exactly 32 bits— the same size as a data word. In keeping
with our design principle that simplicity favours regularity, all MIPS
instructions are 32 bits long.
Structures used in
MIPS
The
MIPS processor is compilation of a lot many structures which are used as blocks
for interconnection. The utilization of all these blocks is explained here.
Program Counter
The purpose of Program
Counter is to deposit the address of the next executing instruction. The input
to program counter is the present address and the output is the next address.
The block diagram of program counter is shown in Figure.5.
Figure.5 Program Counter
Instruction Memory
Figure.6 Instruction
Memory
Adder
The adder is the general circuit which takes two bits as
inputs and gives result the sum of the two bits. The block diagram of adder is
shown in Figure.7.
Figure.7
Adder
Instruction
Decoder Unit
This
unit generally takes input as a 32-bit instruction and outputs all the required
instructions and these specified values are input to next part of circuit. The
block diagram of Instruction Decoder unit is shown in Figure.8.
Figure.8. Instruction
Decoder
Arithmetic Logic Unit
The
ALU is the unit used for computations. This is the basic unit text which
performs all the operations required by the processor.
Figure.9 Arithmetic
Logic Unit
Data Memory
This is the second
memory of the MIPS. This memory can be used for both Read and Write
applications. Hence this circuit can be replaced by a Random Access Memory. The
input is the address and if read signal is enable it reads the data from the
inputs memory location. If the write signal is enable it writes the data into
the input's memory location.
Figure.10 Data Memory
Sign Extend Unit
Figure.11 Sign Extend Unit
Registers
This is the next block presiding the Instruciton Decode. It
is useful for reading the instruciton and performing the reading or writing
operations on the particular memorylocation.
Figure.12
Register Block
Datapath
Datapath can be explained as the interconnections used for
connecting the blocks. When connecting
the blocks we can have two types of implementations.
a)Single
Datapath : This type of datapath an simple datapath. It
is called single as it makes an endeavour to complete instruciton in one clock
cycle .
Disadvantages
When an instruciton is not able to complete in a clock cycle
, it stops immediately giving erroneous result.
To overcome the problem we move on to multi core datapath.
b)
Multicore Datapath : It
is an instant when designer divides the execution of instrucitons into
different clock cycles, Inorder to ensure that even the slowest one of all the
instructiomentaion for its questerity.
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