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Adder's

Adders

  • Half Adder
    IC block
HA block

Half Adder Internal logic
logic 
HA Truth table
functionality

VHDL Code

entity HA is

port(a,b : in std_logic;
s,c : out std_logic);
end HA;
architecture functional of HA is
begin
s <= a xor b;
c <= a and b;
end functional;

Verilog Code

module ha(

output s,
output c,
input a,
input b
);
assign s = a ^ b;
assign c = a & b;
endmodule

Simulation Results
verification phase

  • Full Adder
 IC block
IC of  FA

Internal logic
logic's

Truth Table
functionality
VHDL Code

entity FA is

port(a,b,cin : in std_logic;
s,cout : out std_logic);
end FA;
architecture functional of FA is
begin
s <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (cin and a);
end functional;

Verilog Code

module fa(

output s,
output cout,
input a,
input b,
input cin
);
assign s = a ^ b ^ cin;
assign cout = (a & b)|(b & cin)|(cin & a);
endmodule

Simulation Results
verification phase


  • n-bit general Adder
Block diagram
RCA  for  n-bit
VHDL Code
entity general_adder is
generic(n : integer := 8);
port(x,y : in std_logic_vector(n-1 downto 0);
r : out std_logic_vector(n-1 downto 0);
cout : out std_logic);
end general_adder;
--component is same as in the above half adder program
architecture functional of general_adder is
component FA
port(a,b,cin : in std_logic;
s,cout : out std_logic);
end component;
signal c : std_logic_vector(n downto 0);
begin
c(0) <= '0';
f1: for i IN 0 to n-1 generate
p1: FA  port map(x(i),y(i),c(i),r(i),c(i+1));
end generate;
cout <= c(n);
end functional;

Verilog Code

module general_add(r,cout,x,y,cin);

parameter n = 8;
output [n-1:0] r;
output cout;
input [n-1:0] x;
input [n-1:0] y;
input cin;
assign {cout,r} = x+y+cin;
endmodule

Simulation Results
verification phase

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