32-Bit Multiplier from Dadda through Vedic

Design and Implementation of 32-Bit Multiplier from 8-bit,16-bit Dadda through Vedic

This article covers:

Vedic Concept.
Faster Dadda Multiplication.
Building 32-bit multiplier from Dadda through Vedic.
Simulation results.
Design Summary.
Results.

1. Vedic Concept:
Vedic mathematics is the ancient Indian system of mathematics. It was rediscovered again in the early 20th Century. We know that a Multiplier is a key hardware block in the architecture of either DSP's or microprocessor which defines its speed and power. The multiplier implemented through this vedic technique gives the good results in terms of speed and power considerations. All ancient Indian mathematical works were composed in Sanskrit, usually consisted of a section of Sutras. The Vedic mathematics uses simple simple rules and principles to solve the arithmetic, algebra, trigonometry and geometry problems. This vedic systems is based on 16 vedic sutras. Here, the natural ways of solving the problems is adopted on which human minds work more effectively. This vedic systems have the effective algorithms.

Vedic multiplier is based on the algorithm, called Urdhva Tiryagbhyam which is one of the 16 vedic sutras. The Urdhva refers to vertical and the Tiryagbhyam refers to the cross wise. This Sutra specifies how to handle the n*n order multiplication by smaller order multipliers. The first basic multiplier block required for the implementation of vedic multiplication is 2*2 multiplier. From this basic 2*2 multiplier the 4*4, 8*8, 16*16, 32*32 are developed.

CONSTRUCTION OF A 2*2 VEDIC MULTIPLIER

Step 1: Consider,

Step 2:

Step 3:

Step 4:

Step 5:

Step 6:

The area required for this Vedic multiplier is smaller when compared to other multiplier architecture. This Vedic multiplier becomes complex when the order goes up. Due to its parallel implementation, the realization can be very easy.

2*2 BIT VEDIC MULTIPLIER

4*4 BIT VEDIC MULTIPLIER

A Vedic 4*4 bit multiplier can be developed with the four 2*2 bit vedic multipliers as shown here:

Similarly, with 4*4 bit Vedic multipliers the 8*8 bit multiplier, with 8*8 bit Vedic multipliers the 16*16 bit multiplier, with 16*16 bit vedic multipliers the 32*32 bit multiplier etc., can be constructed.

2. Faster Dadda Multiplication:

The Computational speed of the regular Dadda Multiplier can be enhanced by partitioning the Partial products into two parts. This partitioned partial products can then separately reduced same as regular Dadda multiplier. Finally, these results from two parts are to be merged to get final result.

Here,the two parts are reduced in parallel with the same Dadda reduction procedure stated above. Due to this parallelism approach of reduction the Multiplier is very speed than the custom Dadda Multiplier.

PART 0 Reductions:

This Part 0 Matrix compression takes 17 - [3,2] counters and 6 - [2,2] counters to get final two-rowed Matrix. The final stage is merged with the Carry propagation adder and a 11-bit result is obtained.

PART 1 Reductions:

This Part 1 Matrix compression takes 14 - [3,2] counters and 5 - [2,2] counters to get final two-rowed Matrix. The final stage is merged with the Carry propagation adder and a 8-bit result is obtained.

MERGING OF THE PART 0 & 1 RESULTS:

Here, the first 9 bits in part 0 result is directly carried to the final result(p(0) to p(7)). The Common result part in both part 0 & 1 is added with 3-bit RCA and carried to final result(p(8) to p(10)).

HYBRID ADDER

5-BIT BINARY TO EXCESS-1 CODE CONVERTER

Finally, final result part from p(11) to p(15) is obtained through the Hybrid Adder. Thus,a 16-bit result is obtained.

3.Building 32-bit multiplier from Dadda through Vedic:

From a 8-bit Dadda multiplier, a 32-bit multiplier can be obtained by constructing a 16-bit multiplier first through vedic concept. Then using that 16-bit multiplier through vedic concept the 32-bit multiplier is then obtained.

32-BIT MULTIPLIER FROM 8-BIT DIRECT DADDA THROUGH VEDIC:

Step 1: Develop 8-bit Dadda Multiplier(direct).

Step2: Construction of 16-bit multiplier from 8-bit direct dadda through vedic.

Step 3: Using the above 16-bit multipliers through Vedic a 32-bit multiplier is developed.

Step 4: finally, the 32-bit multiplier is developed as shown in the above.

32-BIT MULTIPLIER FROM 16-BIT DIRECT DADDA THROUGH VEDIC:

Step 1: Develop a direct 16-bit Dadda by reducing the 256 partial products through partitioning into two parts.

Step 2: After obtaining the results from both the parts, merging with hybrid adder gives the 32-bit result.

Step 3: Here, the Vedic concept is used to develop a 32-bit multiplier.

Step 4: finally, the 32-bit multiplier is developed as shown in the above.

A 32-Bit direct dadda multiplier can be obtained by reducing the 1024 partial products through partitioning them to two parts. Finally the results from each part are merged through adder to obtain the 64-bit result.

4. Simulation Results:

1. Simulation results of 32-bit multiplier developed from 8-bit direct dadda through vedic: